The CPU component of the Nexus zkVM’s constraint system is responsible for ensuring that each state transition is correct. In particular, it is responsible for ensuring that the instruction fetch, instruction decode, and write-back stages of the classic RISC pipeline are correct. It also facilitates connecting other stages of the pipeline with their respective constraint circuits.

Concretely, the CPU component performs the following tasks for each CPU cycle:

  • Interacts with the program memory to fetch the next instruction pointed to by the program counter.
  • Decodes that instruction and verifies that it is well-formed.
  • Interacts with the register memory component to read the values associated with the instruction’s operands.
  • Interacts with the execusion component to execute the just-fetched instruction.
  • Interacts with the register memory to perform write-back.

We discuss some of the constraints for this component when we describe our example, but details of all the constraints for this component can be found in Section 4 of the specification.

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