ADDI x10 x8 3
. Moreover, for the sake of this example, let us assume the following about the state of the VM.
ADDI x10 x8 3
instruction at clock cycle , the CPU component will perform the following operations:
ADDI x10 x8 3
from the program memory component;ADDI x10 x8 3
; andADDI x10 x8 3
. Hence, the following holds:
ADDI x10 x8 3
), the CPU component must interact with the program memory to read the instruction stored at the memory location pointed by the program counter. It must also ensure that the program counter is memory-aligned (i.e., a multiple of ).
Remark: Whenever constraints involve trace columns restricted to the same row, we omit the explicit index for readability. For instance, in the description below, we write instead of . All values set in the remainder of this section, unless explicitly specified, apply only to the row indexed by of the corresponding trace column.
In the specification, the CPU interaction with the program memory is captured by a call to the interface with parameters and to obtain . Note that the CPU component does not check the consistency of the program memory, which is handled separately by the program memory component.
In the actual implementation, this interface is not explicitly implemented since the trace columns for , , and are shared between the CPU and program memory components.
As a result of this interaction, the value of these columns will be as follows:
ADDI x10 x8 3
is as follows:
ADDI x10 x8 3
that was fetched from the program memory and checks the correctness of the binary encoding.
To achieve this goal, the prover provides several auxiliary values (advices) to help verify the correctness of the binary encoding. More precisely, the prover will provide the following values:
ADDI x10 x8 3
. This corresponds to the destination register 10
.ADDI x10 x8 3
. This corresponds to the destination register 8
.3
1
.1
.1
.1
.1
.0
.0
.0
.ADDI x10 x8 3
:
0
(bit 0 from )5
(bits 1—4 from )0
(bit 0 from )4
(bits 1—4 from )3
(bits 0—3 from )0
(bits 4—7 from )0
(bits 8—10 from )0
(bit 11 from )1
0
(all the flags on the right have already been set to 0)1
1
1
ADDI x10 x8 3
at the current clock cycle, the CPU component must interact with the execution component.
In the specification, the interaction with the execution memory is captured by a call to the interface with parameters to obtain the value . Since this is an ADD operation, the execution component also updates the value of .
In the actual implementation, this interface is not explicitly implemented since the trace columns for , , , , , and are shared between the CPU and the execution components.
As a result of this interaction, the values of the limbs for will be updated as follows:
ADDI x10 x8 3
instruction at clock cycle , the execution component first enforces that the ADD operation is executed via the following set of constraints:
Since and , in order to satisfy the set of constraints above, it must be the case that: